Design and Analysis of Low Power Generic Circuits in Nano Scale Technology

Power consumption of Very Large Scale Integrated (VLSI) circuits has been growing at an alarmingly rapid rate. This increase in power consumption, coupled with the increasing demand for portable/hand-held electronics, has made power consumption a dominant concern in the design of VLSI circuits today. Traditionally dynamic (switching) power has dominated the total power consumption of VLSI circuits. However, due to process scaling trends, leakage power has now become a major component of the total power consumption in VLSI circuits. Based on the International Technology Roadmap for Semiconductors (ITRS) report, the sub-threshold leakage power dissipation of a chip may exceed dynamic power dissipation at the 65nm feature size. A new approach is considered to reduce leakage power in VLSI design; named as “SLEEPY KEEPER”. Dual Vth values can be applied to sleepy keeper in order to dramatically reduce sub threshold leakage current. For applications spending the vast majority of time in sleep or standby mode requires low area, high performance and maintenance of exact logic state, the sleepy keeper approach provides a new weapon. SLEEPY KEEPER approach is applied to generic logic circuits and obtained results are compared with well established leakage current reduction techniques like SLEEP, STACK, ZIGZAG, SLEEPY-STACK approaches.